The present invention relates generally to routing architectures for use in, for example, programmable logic devices (PLDs). More particularly, this invention relates to improved routing architectures using one or more high speed input/output (I/O) bypass paths.
PLDs are well known as is shown, for example, by Jefferson et al. U.S. Pat. No. 6,215,326 and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Instead of having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those different logic tasks. Many manufacturers of electronic circuitry and systems find the use of PLDs to be an advantageous way to provide various components of what they need to produce. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by or for the end-user, and includes a programmable logic array (PLA), a field programmable gate array (FPGA), an erasable and complex PLD, and the like.
The basic building block of a PLD is a logic element (LE) that is capable of performing limited logic functions on a number of input variables. Each LE in a PLD typically provides a combinational logic function such as a look-up table (LUT), and one or more flip-flops. The input of the flip-flop may programmably be selected to be either the output of the LUT, or one of the input pins of the LE. Other multiplexing circuits may exist to dynamically select between the output of the LUT and one of the inputs of the LE using other logic signals. Moreover, each LE can programmably select as one of the outputs the output of the LUT, which is the combinational output, or the output of the flip-flop, which is the registered output.
To facilitate implementation of complex logic functions, LEs in a PLD are arranged in groups to form one or more logic array blocks (LABs). For example, each LAB in a PLD may include eight LEs, and the LAB may be programmed to provide any one of a plurality of logic functions by using control bits. The LABs in a PLD, meanwhile, are arranged in a one or two dimensional array and are programmably connectable to each other using a PLD routing architecture. The routing architecture of a PLD (e.g., an FPGA), moreover, typically includes an array of signal conductors having programmable interconnections which are used to route data and output enable signals. For example, the routing architecture may include several horizontal and vertical conductor channels, where each of these channels includes one or more horizontal or vertical signal conductors, respectively. Additionally, the conductors in a given channel may span all of the LABs in a given row or column, or rather, may span only a subset of the LABs in the row or column (e.g., 4 LABs). These types of conductors are generally referred to herein as segmented conductors.
The routing architecture of a PLD typically also includes internal conductors associated with (e.g., located inside) each LAB. Additionally, drive circuitry is used to provide inputs to the LEs and route outputs from the LEs to the conductors both within the LAB and outside the LAB. For example, a first set of internal conductors within a LAB may be driven by multiplexers (e.g., one associated with each LE) that select from routing signals outside the LAB, while a second set of internal conductors can be used to carry signals solely generated by LEs within a given LAB.
In order to allow external signals to enter the PLD for processing and to allow logic signals produced by the PLD to be applied to external circuitry, PLDs also include I/O circuitry. For example, a PLD may include I/O blocks and I/O pads for conveying signals from within the PLD to external circuits as well as from external circuits to within the PLD. These I/O blocks and I/O pads are typically arranged at the periphery of a chip, and include various connections to the routing architecture of the PLD. Moreover, in typical use, a portion of the I/O pads can be configured for input purposes and a different portion can be configured for output purposes. There may also be, for example, some pins associated with I/O pads 170 that are used as bidirectional pins which will dynamically change from input pins to output pins.
In many conventional PLDS, such as an FPGA, a signal traveling in either direction between an LE and an I/O pad passes through a number of components (e.g., multiplexers, signal conductors and programmable interconnections of signal conductors) to reach its destination. Meanwhile, each of these components adds a respective delay to the signal transfer process, sometimes resulting in a prohibitively large propagation delay (e.g., the pin-to-pin data transfer speed may not be fast enough to support certain applications) for the PLD.